Application of a Smart Gate Driver to Detect Aging in SiC Power MOSFETs

In this paper we present an integrated smart gate driver (SGD) capable of in-operation detection of SiC power MOSFET aging. The SGD IC monitors the discrete time differentiated (DTD) gate voltage slope, $\Delta V_{GS}$ , to identify the time to start of the Miller plateau, $t_{1}$ , during turn-on. Under known operating conditions, the value of $t_{1}$ can be used as an aging indicator to detect changes in the Miller plateau due to threshold voltage shifts. A synthesized digital central control unit (CCU) within the SGD can adjust the gate drive profile and gate drive bus voltage ( $V_{DR}$ ) based on the aging-induced changes in $t_{1}$ . We demonstrate that following 200 hours of high-temperature gate bias (HTGB) at 200 °C, $V_{DR, stress}=30\ \mathrm{V}$ , aging-induced gate degradation of a 1.2 kV 75A SiC MOSFET results in a decrease in drain current ( $I_{D}$ ) by 1.5%. An increase in $V_{\text{MP}}$ by 0.5 V can restore $I_{D}$ by 1.7% to pre-aged levels. This is achieved by adjusting the digital pulse width modulation (PWM) duty cycle of the on-chip DC-DC boost converter.