Implementation of dual capture data storage based on a high-speed data acquisition unit

With the rapid development of high-speed data capture technology, the performance of data process, analysis, and storage in the data acquisition unit has become a vital part of the data acquisition system. Especially, the dual capture mode is quite important function for a long-time waveform analysis and special points catching. Because of its high demand for high-speed, very-deep storage and risk of address hopping, it is difficult to satisfy. The objective of this article is to design and implement a high-speed data acquisition unit based on a field programmable gate array with the realization of the dual capture mode and the improvement of the data storage efficiency. Separate data and address control mechanisms are used in the method to store processed points and original data in on-chip resources. This method greatly reduces the resource occupancy rate and is suitable for high-speed digital acquisition modules. By the proposed design introduced in the article, experimental results show that the high-speed dual capture data storage speed could reach 1.6GSa/s with a 0% error rate.