A 56Gb/s De-serializer with PAM-4 CDR for Chiplet Optical-I/O

This paper presents a 56Gb/s de-serializer with PAM-4 CDR for chiplet optical-I/O in 28nm CMOS. There are two channels in this chip. Each channel consists of a high-performance analog front end (AFE) and a half-rate clock and data recovery (CDR) circuit based on a digital phase interpolator and digital loop filter. To provide 28-GHz clock signals to both channels, a clock distribution circuit is integrated. Experimental results show that the proposed de-serializer recovers a 56Gb/s PAM-4 input signal with channel loss, achieving an output swing of 1.01-Vppd and 760ps RMS jitter.