Gate Driver Switching Noise Propagation Study for Medium Voltage SiC-based Power Electronics Building Blocks

The fast dv/dt rate of the silicon-carbide (SiC) devices generates switching noise propagated inside the converter and may corrupt the critical signals on the gate driver PCB and cause potential malfunction (such as false-triggering). The gate drivers for PEBBs employ complex design and can achieve comprehensive functionalities. Prior studies have proposed different approaches to minimize the common-mode (CM) current on the gate driver PCB, but the mechanism how the CM current causes the gate driver malfunction remains unknown. This paper proposed a three-level methodology to study the noise propagation on gate drivers under high dv/dt, particularly how the CM current on ground planes is linked to the noise on the signal traces and thus the differential mode noise at the input of ICs. As a case study, the proposed methodology is applied to a gate driver that is designed for 10 kV power devices. Several critical traces are selected for study, and experiments are designed and conducted to validate the proposed methodology and investigate the factors that influence the noise propagation.