Comparison of synthesis strategies in terms of switching activity

The article presents a comparison of two synthesis strategies in terms of the Switching Activity (SW) parameter. The value of this parameter influences the dynamic power consumption. Two oriented to LUT-based FPGA synthesis strategies were compared. The first is aimed at minimizing the number of LUT blocks, and the second is at minimizing the number of logic levels. Both strategies have been implemented in the DekBDD system. The essence of these strategies is the modification of the method of estimating the effectiveness of decomposition at each stage of its implementation. The article contains the results of experiments performed on a popular set of benchmarks. The results of the experiments show that the synthesis strategy aimed at minimizing the number of blocks leads to systems with lower dynamic power consumption.