Designing of an 8 x 8 Multiplier with New Inexact 4:2 Compressors for Image Processing Applications

Inexact computing brings benefits to error-tolerant applications, including multimedia and signal processing. Although inexact computing reduces precision, it provides meaningful and faster results yet, with lower energy consumption and lower system architecture complexity. We introduce two 4:2 inexact compressors into the unsigned 8 x 8 multiplier circuit by truncating and combining the presented compressors, which in terms of dynamic power shows 25 and 57.14%, respectively, improvement in comparison with the exact multiplier and the best value of similar models. The proposed multiplier with the truncating and combining method and the second proposed compressor shows 7.78 and 67.97% improvement in the MED and PDUEP, respectively, improvement in comparison with the best value of similar models. In design of the transistor level, the proposed models improve the power up to 0.007 mu W. In the image processing application, the proposed multipliers with the truncating and combining method, improve the PSNR up to13.23 and 16.17%, respectively, and improve the SSIM up to 0.90 and 0.94%.The routing and mapping of the proposed circuits are conducted using the hybrid method to improve the evaluation criteria for image processing applications. The validity of the performance of the proposed multipliers are examined with simulations of FPGA circuits (Virtex-6 family) and ASIC circuits (RF_CMOS 0.18 mu m), and simulation of applications in image processing is carried out in MATLAB software.