Stacked SiGe/Si I/O FinFET device preparation in a vertically stacked gate-all-around technology

In this work, a stacked SiGe/Si input-output (I/O) FinFET device preparation with an optimized thermal budget and atomic layer deposition (ALD) SiO2 gate dielectric is investigated. First, a vertical and smooth profile of the stacked SiGe/Si fin without obvious Ge diffusion and SiGe oxidation is maintained by developing an optimized STI densification process using rapid thermal annealing (RTA) of 850 °C for 30s. Then, a high-quality ALD SiO2 with thickness of 3 nm suitable for the gate dielectric layer of I/O device is verified based on MOS capacitance (CAP) structure. Finally, a stacked SiGe/Si I/O FinFET targeting 1.8V operating voltage (VDD) is successfully prepared with good physical structure and electrical characteristics. Meanwhile, its maximum operating voltage (Vmax) for a 10 years lifetime at a failure rate of 0.01% can reach to 2.03V. Therefore, these newly developed processes are practical for the stacked SiGe/Si I/O FinFET device in a vertically stacked GAA technology.