A 300-GHz 52-mW CMOS Receiver With On-Chip LO Generation

A fully integrated receiver employs a heterodyne architecture with 270- and 27-GHz local oscillators to alleviate phase mismatch issues. The system incorporates three on-chip phase-locked loops (PLLs) to generate the local oscillator phases for both downconversions. Realized in 28-nm CMOS technology, the prototype exhibits a noise figure of 16–20 dB, a gain of 17–21 dB, and a 1-dB compression point of −17.3 dBm. The phase noise (PN) of the 270-GHz PLL is −105 dBc/Hz at 10-MHz offset, amounting to an integrated jitter of 106 fs from 10 kHz to 10 MHz.