How Fault-Tolerant Quantum Computing Benefits from Cryo-CMOS Technology.

H.-L. Chiang, R. A. Hadi,J.-F. Wang, H.-C. Han,J.-J. Wu, H.-H. Hsieh, J.-J. Horng, W.-S. Chou, B.-S. Lien,C.-H. Chang,Y.-C. Chen,Y.-H. Wang,T.-C. Chen,J.-C. Liu,Y.-C. Liu,M.-H. Chiang,K.-H. Kao, B. Pulicherla, J. Cai,C.-S. Chang,K.-W. Su, K.-L. Cheng, T.-J. Yeh, Y.-C. Peng,C. Enz,M.-C. F. Chang,M.-F. Chang, H.-S. P. Wong, I. P. Radu

VLSI Technology and Circuits（2023）

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摘要

Given the limited space and cooling capacity in dilution refrigerators, it is challenging to scale the number of qubits for a fault-tolerant quantum computer (QC). In this paper, we study a custom-scaled CMOS technology to overcome the constraints in the dilution refrigerators. With Cryo-Design/ Technology CoOptimization (Cryo-DTCO) in an advanced node, one can then reduce the control power from 26.8 mW/ qubit to 8.4 mW/ qubit $(\sim 0.31 \times)$. Projections suggest this may be sufficient to enable error corrections via surface codes for fault-tolerant computing.

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