A 65nm 60mW Dual-Loop Adaptive Digital Beamformer with Optimized Sidelobe Cancellation and On-Chip DOA Estimation for mm-Wave Applications.

VLSI Technology and Circuits(2023)

引用 0|浏览6
暂无评分
摘要
This paper demonstrates an mm-wave baseband digital beamformer that fully integrates an adaptive sidelobe canceller and on-chip direction of arrival (DOA) estimation. To achieve high energy-efficiency, the DOA estimation loop preemptively adjusts the weights of the phase rotators at the front of the SAR-ADCs, which enables the sidelobe cancellation loop to be implemented with a straightforward structure. For efficient ESPRIT DOA estimation, CORDIC-based QR-iteration is employed to solve eigenvalue decomposition, thus circumventing the need for complex matrix computation. The adaptive beamformer implemented in 65nm CMOS dissipates 60mW at 100MHz while occupying 0.64mm 2 on-chip area. The energy efficiency is 600(330) pJ/symbol with (without) DOA estimation.
更多
查看译文
关键词
2 on-chip area,65nm 60mW dual-loop adaptive digital beamformer,65nm CMOS dissipates 60mW,adaptive beamformer,adaptive sidelobe canceller,arrival estimation,CORDIC-based QR-iteration,DOA estimation loop,efficient ESPRIT DOA estimation,energy efficiency,frequency 100.0 MHz,high energy-efficiency,mm-wave applications,mm-wave baseband digital beamformer,on-chip direction,On-Chip DOA Estimation,optimized sidelobe cancellation,power 60.0 mW,sidelobe cancellation loop,size 65.0 nm
AI 理解论文
溯源树
样例
生成溯源树,研究论文发展脉络
Chat Paper
正在生成论文摘要