III-V Devices and Technology for CMOS

In this chapter, advances in the use of III-V materials for both n- and p-MOSFET devices will be reviewed including progress in gate stack technology and its associated reliability. For the full potential of III-V to be realized in advanced CMOS technology nodes, it must be integrated on 300 mm wafers in order to leverage the benefits of the high-volume manufacturing techniques and toolsets used in advanced Si-CMOS manufacturing. Therefore, a strong emphasis in this chapter is placed on how III-V devices may be integrated onto a Si platform in order to be deployed in a manufacturable VLSI-compatible flow.