Record 7(N)+7(P) Multiple V(T)s Demonstration on GAA Si Nanosheet n/pFETs using WFM-Less Direct Interfacial La/Al-Dipole Technique

2022 INTERNATIONAL ELECTRON DEVICES MEETING, IEDM(2022)

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摘要
In this paper, for the first time, we have realized record 7(N)+7(P) multiple threshold voltages (Multi-V(T)s) on horizontal gate-all-around (GAA) Si nanosheet (SiNS) n/pFETs using work-function-metal-less (WFM-less) direct interfacial La/Al-dipole technique, regardless of the sheet-to-sheet spacing (T-sus) pinch-off in stacked channels. Owning to higher dipole intensity in ultra-thin high-k dielectric (HK) films obtained by ALD in-situ direct dual dielectric La-/Al-dipole (D-4) control between adjacent NSs, both nFETs and pFETs have achieved 7 V(T)s (1 RVT, 3 HVT and 3 LVT) with good uniformity and discrimination even in WFM-less gate stack. The maximum V-T tuning ranges reach 1105 mV/873 mV and the minimum discriminable Delta V-T over 83mV/76mV for n/pFETs, respectively, exhibiting great multi-V(T)s application advantages for future high performance and low power GAA SiNS CMOS process.
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ALD in-situ direct dual dielectric dipole control,dipole intensity,GAA silicon nanosheet nFETs,GAA silicon nanosheet pFETs,HK films,horizontal gate-all-around nanosheet pFETs,horizontal gate-all-around nanosheet nFETs,La-Al/int,low power GAA SiNS CMOS process,multiple threshold voltages,multiVT application,record 7(N)+7(P) multiple VTs,sheet-to-sheet spacing pinch-off,Si/int,stacked channels,ultra-thin high-k dielectric films,voltage 1105.0 mV,voltage 76.0 mV,voltage 83.0 mV,voltage 873.0 mV,WFM-less direct interfacial dipole technique,WFM-less gate stack,work-function-metal-less direct interfacial dipole technique
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