Evaluating Fault-Tolerant Techniques on COTS RISC-V NOEL-V Processor in Zynq UltraScale+ FPGA Under Proton Testing

This work evaluates different fault tolerance techniques on the RISC-V NOEL-V processor synthesized into the SRAM-based Zynq UltraScale+ field programmable gate array (FPGA) under proton testing. We investigate the effect of the cache size on the reliability of the processor and the use of scrubbing combined with triplication, duplication with comparison (DWC), and cache refreshing. The design area in SRAM-based FPGAs directly affects the soft error cross section. However, results show that increasing the L1 cache size and using the correct combination of mitigation techniques reduces the overall single event effect (SEE) susceptibility of the RISC-V NOEL-V processor.