Substrate noise mitigation using high resistivity base silicon wafer for a 14 GHz VCO on 28 nm FD-SOI

This paper studies the impact of substrate resistivity on the sideband spurs generated at the output of a 14 GHz voltage-controlled oscillator (VCO) because of noise signal propagation through the substrate. A VCO has been designed in the 28 nm fully depleted Silicon-on-Insulator (FD-SOI) technology and implemented on a standard ($15~\Omega.\mathrm{cm}$), a high resistivity ($3~\mathrm{k}\Omega.\mathrm{cm}$ with parasitic surface conduction) and a trap-rich ($3~\mathrm{k}\Omega.\mathrm{cm}$ without parasitic surface conduction) silicon base wafer. The output spectrum of the VCO (around $f_{osc}$) when injecting a 10 dBm noise signal at a frequency of 10 MHz ($f_{noise}$) into the substrate is simulated, showing spurs generated at $f_{\text {osc }} \pm f_{\text {noise }}$, and at other higher-order modulation products. The results obtained on the high resistivity substrate show a reduction of 10 dB of the $f_{osc} \pm f_{noise}$ sideband spurs compared to those on the standard resistivity substrate. The spurs are further reduced by more than 90 dB when a trap-rich SOI wafer is used. Those results highlight the important impact of substrate resistivity and parasitic surface conduction on the signal integrity of CMOS VCOs.