High-Resolution Fractional Digital Frequency Divider using a Binary-Rate Multiplier

An enhanced fractional digital frequency divider using a Binary Rate Multiplier (BRM) is presented in this paper. The proposed architecture improves the prior BRMs performance by using a double-edge synchronous operation mode, that provides better periodical output pulse uniformity. Two input Binary Words are used to set the frequency division ratio, adding extra flexibility for fractional division ratios. Its simple architecture makes it an attractive solution for high-frequency and low-power applications. The features and limitations of the proposed BRM are evaluated in MATLAB (R) and compared with its prior solutions.