A 4 GBaud 5 Vpp Class-B Pre-Driver Design for GaN-Based Switching Power Amplifier in 22 nm SOI-CMOS Utilizing LDMOS

NEWCAS(2023)

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摘要
The paper presents a highly power efficient class-B LDMOS-based pre-driver, implemented in a 22nm FDSOI CMOS process. The driver generates an output voltage swing of 5. 5V at a data-rate of 4 GBaud for GaN-based switching power amplifier with an estimated capacitive load impedance of 0.35 pF. This is achieved by utilizing monolithical integrated LDMOS devices with a breakdown voltage of 6.5 V, available in the deep submicron state-of-the-art CMOS process, which are driven by an inverter-chain consisting of 2V thick-oxide devices with an active back-gate control to implement a duty-cycle calibration. The proposed design achieves rise- and fall-times of 70ps and 40 ps, respectively. The total power consumption is below 140 mW from a triple 5. 5V, 3.5V and 2V power supply for a 4 GBaud NRZ PRBS input. This greatly improves the state-of-the-art power efficiency for CMOS-based GaN power amplifier predriver.
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关键词
CMOS, 22nm FDSOI, LDMOS, back-gate control, GaN, gate driver, digital power amplifier
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