A novel technique for flit traversal in network-on-chip router

With booming intricacy in applications, optimizing latency is a key requirement in Network-on-Chip (NoC). Bypassing the routers in the intermediate path, the Single Cycle Multi-Hop Asynchronous Repeated Traversal (SMART) NoC is offered as a solution. However, SMART requires a bypass arrangement, contributing to additional wires and stages in the pipeline. In this paper, the Turn-to-west-first technique is used to establish express bypass channels where all the requests for bypass are jointly sent with the flits. The techniques including adaptive routing, combined wormhole switching, and virtual cut-through have been integrated into the router design. The mathematical modeling is done to calculate the wire overhead for the proposed design. Based on these considerations, a novel router architecture is designed to allow the flits to traverse both in one or two-dimensional paths without latching in any bypass router. The presented design has been compared with the baseline router and other popular bypass methods for the average packet latency and wire overhead. Both the synthetic traffic and specific traces of realistic traffic taken from the PARSEC benchmark suite have been considered for evaluation of the proposed design. In comparison to SMART NoC around 85% of the additional wires are reduced and over 40.51% reduction in latency is observed. The latency-optimized NoC is suitable to be used for high-speed applications.