P* Admissible Thermal-Aware Matrix Floorplanner for 3D ICs

Over the past decade, three-dimensional (3D) integrated circuits (ICs) have matured as a promising solution for high-performance computing systems. Achieving high power density (>1 W/mm ² ), however, poses a critical thermal management challenge, as heat is prone to be trapped within the layers of the 3D structure. Early-stage power-aware floorplanning is crucial to address thermal challenges, supporting the evaluation of multiple design alternatives. In this paper, a P* admissible thermally aware floorplanning algorithm for 3D ICs is proposed. The operation principle of the algorithm is based on storing and manipulating the data of the functional blocks in a matrix form, supporting polynomial optimization and packing time. Simulation results on standard benchmarks (MCNC and GSRC) exhibit a significant improvement in key performance metrics. A reduction in area, temperature, and runtime of up to, respectively, 10.1%, 17.7%, and 89.6% are observed, as compared to the state-of-the-art.