HierArch: A Cluster-Based DNN Accelerator with Hierarchical Buses for Design Space Exploration

With the increasing intensity of deep neural network (DNN) workloads, developing various hardware accelerators and their estimation tools have become vital to tackle this challenge. Modern DNN accelerators often develop a cluster that involves multiple processing arrays, therefore, the design of interconnections for connecting processing arrays has emerged as a crucial component in achieving high performance. This paper proposes a novel architecture of cluster-based accelerator architecture with high-level synthesis, enabling rapid exploration of the design space for scalable interconnection bandwidth, cluster size, and PE array size. Additionally, we leverage tag data and work modes to introduce flexibility in data communication without restricting the type of dataflow and data mapping. Through the evaluation, our proposed architecture demonstrates performance improvements ranging from 14% to 67.8% for different neural network models, achieved simply by adjusting the cluster size.