Compute SNR-boosted 22 nm MRAM-based In-memory Computing Macro using Statistical Error Compensation

The accuracy of eNVM in-memory computing (IMC) designs is primarily limited by analog non-idealities. This paper presents an MRAM IMC macro in 22nm equipped with offset-compensating current sensing and a low-overhead statistical error compensation (SEC) block to boost its compute signal-to-noise ratio (SNR). The compute SNR reduces with an increase in inner-dimension of the MVM. An SEC-enabled SNR boost of 2.7-to-6 dB is obtained over different operating points. This boost can be traded-off to realize a $ 5\times$ decrease in energy/lb-OP including an SEC energy overhead of 0.S%. Finally, we demonstrate an SEC-enabled neural network (NN) accuracy boost from 74.8% to 82.0% for CIFAR-10 over ResNet20 without on-chip training.