A 4.27TFLOPS/W FP4/FP8 Hybrid-Precision Neural Network Training Processor Using Shift-Add MAC and Reconfigurable PE Array

This paper presents an energy-efficient FP4/FP8 hybrid-precision training processor. Through hardware-software co-optimization, the design efficiently implements all general matrix multiply (GEMM) operations required for training using only shift-add multiply-accumulate (MAC) units. The reconfigurable processing element (PE) array further improves efficiency by significantly reducing on-chip memory access. The on-chip convolution decomposition technique supports a wide range of kernels using simple homogeneous data routing. Fabricated in 40nm CMOS, the processor achieves 2.61TFLOPS/W real-model efficiency for ResNet-18 training, outperforming prior art by 59%.