A 12b 1GS/s Pipelined ADC with Digital Background Calibration of Inter-stage Gain, Capacitor Mismatch, and Kick-back Errors

This work proposes a novel correlation-based digital background calibration algorithm that altogether calibrates the inter-stage gain, capacitor mismatch, and kick-back errors with low hardware overhead and simple control logic. A prototype 12b1GS/s pipelined ADC equipped with the proposed calibration technique achieves >60dB SNDR and >80dB SFDR across the entire Nyquist zone.