Investigating charge traps in MoTe₂ field-effect transistors: SiO₂ insulator traps and MoTe₂ bulk traps

Two-dimensional material-based field-effect transistors are promising for future use in electronic and optoelectronic applications. However, trap states existing in the transistors are known to hinder device performance. They capture/release carriers in the channel and lead to hysteresis in the transfer characteristics. In this work, we fabricated MoTe2 field-effect transistors on two different gate dielectrics, SiO2 and h-BN, and investigated temperature-dependent charge trapping behavior on the hysteresis in their transfer curves. We observed that devices with SiO2 back-gate dielectric are affected by both SiO2 insulator traps and MoTe2 intrinsic bulk traps, with the latter becoming prominent at temperatures above 310 K. Conversely, devices with h-BN back-gate dielectric, which host a negligible number of insulator traps, primarily exhibit MoTe2 bulk traps at high temperatures, enabling us to estimate the trap energy level at 389 meV below the conduction band edge. A similar energy level of 396 meV below the conduction band edge was observed from the emission current transient measurement. From a previous computational study, we expect these trap states to be the tellurium vacancy. Our results suggest that charge traps in MoTe2 field-effect transistors can be reduced by careful selection of gate insulators, thus providing guidelines for device fabrication.