25Gbps Automotive Ethernet: System PHY Characterization of ESD Based EM Interferences

2023 IEEE 28th International Conference on Emerging Technologies and Factory Automation (ETFA)(2023)

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Whereas Automotive Ethernet Physical Layer (PHY) Integrated Circuits (ICs) are typically qualified to ensure Electrostatic Discharge (ESD) robustness, an in-vehicle system-level ESD robustness is feasible only if the interactions between the various system components upon an ESD event are comprehensively considered and characterized accordingly. For these characterizations, the system PHY Signal Integrity (SI) and ElectroMagnetic Compatibility (EMC) aspects are at the forefront to validate the technical feasibility of the Electronic Control Unit (ECU). Towards high-speed ECU Printed Circuit Board (PCB) design for 25GBASE-T1(25Gbps Automotive Ethernet), system SI retention and prevention of ElectroMagnetic Interference (EMI) become even more crucial. This primarily results from having higher signal bandwidth (i.e., Nyquist frequency) and faster signal rise/fall time. In this study a detailed ESD validation considering the two critical ESD current paths in an ECU PCB implementation for 25GBASE-T1 for both powered and unpowered systems is discussed. A 25GBASE-T1 ECU Media Dependent Interface (MDI) PCB design concept is manufactured and utilized as test boards. The ESD current characteristics through the PCB Shield-GND (SG) termination are investigated and characterized in detail. Furthermore, to investigate also potential sources of ESD based EMI, an approach to combat EMI coupling during an ESD event within the ECU SG discharge current path is proposed.
Automotive Multi-Gigabit Ethernet,IEEE 802.3cy,25GBASE-T1,PHY,ECU,PCB,MDI,ESD,EMI,Return Loss
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