Accelerating Network Coding with Programmable Switch ASICs

Random Linear Network Coding holds great potential for enhancing the performance of mega-constellation networks. However, its implementation brings several challenges such as complexity in matrix operations, bandwidth limitations, and increased latency. Although some CPU- and GPU-based solutions have achieved sufficient coding throughput, the gateway stations of satellites require processing rates greater than 10 Gbps while maintaining sub-millisecond delays, which is a challenge with current solutions. In this study, we present and assess efficient RLNC encoding strategies for programmable hardware pipelines, such as the widely adopted Tofino chip with multiple programmable packet parsers and match-action stages. Our approach differs from existing RLNC implementations by offloading the demanding matrix operations from the CPU to the programmable network switch hardware pipeline. Additionally, we optimize logical table ID and other resource utilization by scheduling matrix multiplications across multiple stages. We performed a preliminary evaluation of our design on the Tofino switch and observed a significant improvement in RLNC encoding latency, with a reduction to sub-millisecond levels. Moreover, our design outperforms state-of-the-art solution in terms of throughput when the generation size is greater than 100.