A Bulk-Controlled 12 GS/s Track and Hold Amplifier with >58 dBc SFDR and >53.5 dB SNDR in 22 nm FD-SOI CMOS

2023 18th European Microwave Integrated Circuits Conference (EuMIC)(2023)

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摘要
This paper presents a highly energy-efficient wideband 2x time-interleaved 12 GS/s track-and-hold amplifier fabricated in a 22 nm FD-SOI CMOS process. A single swing-enhanced bulk-controlled front-end buffer is adopted to achieve a signal swing of 0.8 Vppd, while minimizing bandwidth mismatch and kickback effects. Each bootstrapped 6 GS/s top-plate sampler takes advantage of an active bulk-voltage modulation scheme, improving the measured tracking bandwidth of 15 GHz during the on-phase while mitigating leakage-current effects in the off-state. The track-and-hold amplifier utilize offline TI calibration and maintains a single-tone SFDR and SNDR of 58 dBc and 53.5 dB respectively across the entire Nyquist band, while two-tone-test reveals an IM2 and IM3 tone of 63.5 and 66 dBFS respectively. The estimated clock-jitter is only sigma = 28 fs considering both the internal track-and-hold amplifier clock path as well as the external clock source. The total power consumption equals 142mW, drawn from a triple 2V, 0.9V, and -0.8V power supply.
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关键词
TaH,FD-SOI,ADC,wide-band,TI,front-end
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