MicroNAS: Memory and Latency Constrained Hardware-Aware Neural Architecture Search for Time Series Classification on Microcontrollers
CoRR(2023)
摘要
Designing domain specific neural networks is a time-consuming, error-prone,
and expensive task. Neural Architecture Search (NAS) exists to simplify
domain-specific model development but there is a gap in the literature for time
series classification on microcontrollers. Therefore, we adapt the concept of
differentiable neural architecture search (DNAS) to solve the time-series
classification problem on resource-constrained microcontrollers (MCUs). We
introduce MicroNAS, a domain-specific HW-NAS system integration of DNAS,
Latency Lookup Tables, dynamic convolutions and a novel search space
specifically designed for time-series classification on MCUs. The resulting
system is hardware-aware and can generate neural network architectures that
satisfy user-defined limits on the execution latency and peak memory
consumption. Our extensive studies on different MCUs and standard benchmark
datasets demonstrate that MicroNAS finds MCU-tailored architectures that
achieve performance (F1-score) near to state-of-the-art desktop models. We also
show that our approach is superior in adhering to memory and latency
constraints compared to domain-independent NAS baselines such as DARTS.
更多查看译文
AI 理解论文
溯源树
样例
生成溯源树,研究论文发展脉络
Chat Paper
正在生成论文摘要