Experimental assessment of gate-induced drain leakage in SOI stacked nanowire and nanosheet nMOSFETs at high temperatures

•The gate-induced drain leakage (GIDL) in stacked nanowire and nanosheet transistors at high temperatures of operation is experimentally assessed for the first time.•The temperature rise increases the current due to GIDL and its dependence on the device width.•Temperature rise increases band-to-band generation in the overlap region between the drain and the gate, causing a larger GIDL current.•Device width increase weakens coupling, allowing the region where band-to-band tunneling occurs to extend to the interior of the undoped body, contributing to the rise of GIDL.