Ultra High Density Low Temperature SoIC with Sub-0.5 m Bond Pitch

The future continuation of Moore's Law will require a combination of transistor scaling as well as system scaling through the utilization of 3D chip stacking. Transistor scaling in advanced process nodes has become increasingly challenging and is projected to face difficulties in maintaining historical trends in Moore's Law scaling. System scaling utilizing 3D chip stacking in conjunction with transistor scaling offers an enticing avenue to continue density and power/performance scaling along historical trends. 3D chip stacking utilizing system on integrated chip (SoIC) has demonstrated high density interconnects and energy efficient performance. SoIC has enabled new architectures such as memory-on-logic stacking and logic-on-deep trench capacitor (DTC) with exceptional energy efficient performance (EEP). Further scaling of the 3D interconnect pitch into the sub-micron regime will lead to increasing EEP and enable new 3D chip stacking architectures such as partitioning 2D functional blocks into 3 dimensions. These new architectures are anticipated to provide significant gains in computing performance, bandwidth, and transistors per unit area. In this paper we present a bond pitch of 400 nm in a wafer-on-wafer low temperature SoIC configuration. At the chip-to-chip interface I/O interconnect level, the EEP is over 2000 times greater than SoIC currently in mass production. Process challenges and associated mitigation strategies resulting in excellent electrical and reliability performance will be addressed. In particular, we have achieved the required tight bonding overlay control for highly scaled bond pads.