TICA: Timing Slack Inference and Clock Frequency Adaption Technique for a Deeply Pipelined Near-Threshold-Voltage Bitcoin Mining Core

This article presents a timing slack inference and clock frequency adaption technique, named TICA, to mitigate the large and pessimistic timing guardband reserved for process, voltage, and temperature (PVT) variations in deeply pipelined ultra-low-voltage (ULV) circuits. TICA can perceive the dynamic PVT variations of a circuit with in situ cycle borrowing detectors, then infer its runtime timing slack, and adjust the clock frequency accordingly to minimize the redundant timing margin timely. Therefore, with TICA, a circuit can maintain a small amount of positive timing slack, free from the costly timing error correction process required in conventional in situ timing error detection and correction (EDAC)-based circuits. For error-tolerant applications, TICA can also keep the circuit's timing slack at a small negative level for further energy efficiency and throughput improvements. Moreover, an inference-accuracy-driven in situ cycle borrowing detector insertion method is presented, which greatly reduces the insertion rate and the associated timing error detection overheads by leveraging the monotonic relationship between the timing slack and the number of cycle borrowing events. We implement TICA in a near-threshold-voltage (NTV) bitcoin mining core featuring a 64-stage deeply pipelined SHA256 engine in a 28-nm process, with only 0.59% in situ detector insertion rate and 1.4% area overhead. Silicon measurements show 4.2 x throughput improvements or 19.3% energy savings without any timing error compared to the baseline margined for a 10% $V_{\mathrm{DD}}$ drop, as well as additional 35.7% throughput gains or 10.6% energy savings at 0.3 V when maintaining the error rate of SHA256 computing results at 1%.