Transistor Self-Heating-Aware Synthesis for Reliable Digital Circuit Designs

With the continuous scaling in technology nodes, the transistor self-heating effect (SHE) emerges as a growing threat to circuit reliability. Increasingly confined transistor structures and advanced materials exacerbate thermal insulation, concealing temperature hotspots in the transistor's channel. Without the consideration of these increased temperatures, reliability effects such as aging will be underestimated, putting the circuit at risk. In this work, we propose a novel design flow that enables designers to extract accurate SHE temperatures at the circuit level and harden their design with SHE-aware synthesis. Our approach employs customized standard cell libraries to convey SHE information and guide logic synthesis toward SHE-resilient designs. Using our approach, we demonstrate effective suppression of SHE in circuits by up to 50 %, trading off improved SHE resilience against timing, power, and area goals. In addition, our SHE analysis allows for accurate estimation of timing guardbands, reducing unnecessary pessimism of conventional approaches by over 50 %.