An Adjustable P-Region Potential SiC Trench MOSFET with Improved High-Frequency and Short-Circuit Performance

A silicon carbide (SiC) trench MOSFET featuring an adjustable P-region potential (AP-TMOS) is proposed and investigated to improve high frequency and short-circuit performance in this article. A P/N-base layer is embedded in the trench bottom to introduce a P-region portion at the trench corner. The P-region is at a floating potential due to the hole barrier formed in the fully depleted P-base during ON-state conduction of AP-TMOS, and P-region is grounded by the undepleted region of the P-base during OFF-state operation. Compared with the conventional SiC trench MOSFET (C-TMOS), AP-TMOS shows about 23% reduction of the specific ON-resistance because of the shrinkage of JFET depletion layer caused by the floating P-region. Furthermore, the Miller capacitance and gate–drain charge of AP-TMOS are 4.7 pF/cm2 and 51.1 nC/cm2, which are improved by about 2.4 and 1.7 times compared with C-TMOS owing to the reduced overlapping area between gate and drain contact. The short-circuit withstand time of the proposed TMOS with the adjustable P-region potential increases from 4 to $6~\mu \text{s}$ under 800-V dc bus voltage in comparison with C-TMOS. Finally, an analytical model for the hole barrier height has been discussed for AP-TMOS.