An Active Gate Driver Architecture for Simultaneous Transient and Steady-State Currents Balancing for Silicon Carbide Power Modules in Parallel

Silicon Carbide (SiC) MOSFETs are increasingly being adopted in high power applications. Due to the limitations of the current capabilities, sometimes SiC MOSFETs need to be paralleled to achieve required current needs. This may lead to imbalanced current sharing issues between paralleled modules or devices. An active gate driver (AGD) concept with a novel steady-state current balancing method is proposed in this work in an attempt to solve these issues. The concept relies on suppressing the transient imbalance current by introducing a time delay between gate voltages of different paralleled MOSFETs, while incorporating a novel method to mitigate the steady-state imbalance current by applying pulse width modulation (PWM) between two fixed voltage rails provided by the AGD. Comparative loss analysis was performed to verify the effectiveness of the concept under different conditions. The proposed method was realized using a simple hardware architecture and was proven to provide an effective solution to both imbalance current issues in parallel connected SiC MOSFETs.