Comparison of the Simulated Performance of Divider Controllers for Fractional-N Frequency Synthesizers

2023 34th Irish Signals and Systems Conference (ISSC)(2023)

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摘要
Fractional-N phase locked loops (PLLs) are widely used in electronic systems. The architecture of the divider controller has a significant influence on the performance of a fractional-N frequency synthesizer. The divider controller modulates the instantaneous division ratio of the multi-modulus divider in the feedback path. It works by performing quantization on its input signal. The process of quantization introduces noise. Although the quantization noise and its running sum can be made spur free, they are subjected to nonlinear distortions which results in spurious tones in the output signal. As spurious tones are undesired, different divider controllers have been promoted to reduce nonlinearity-induced spurs. Multi-stage noise shaping (MASH), Enhanced nonlinearity-induced noise performance (ENOP), Successive requantizers (SR), and Multi-stage noise shaping structure-successive requantizer (MASH-SR) are four divider controllers that have demonstrated spur immunity after polynomial distortion. This paper compares the simulated performances of these four divider controllers using MATLAB ® . Polynomial and piecewise-linear (PWL) nonlinearities are considered. We show that ENOP P3 exhibits the best performance among the five different divider controllers that are considered in this paper.
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关键词
Phase locked loop (PLL), Fractional-N frequency synthesizer, Digital delta-sigma modulator (DDSM), Multi-stage noise shaping (MASH), Enhanced nonlinearity-induced noise performance (ENOP), Successive requantizers (SR), Multi-stage noise shaping structure-successive requantizer (MASH-SR)
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