17.1 A 2x-lnterleaved 9b 2.8G8S/s 5b/cycle SAR ADC with Linearized Configurable V2T Buffer Achieving >50dB SNDR at 3GHz Input

By increasing the number of bits in each conversion cycle, the sampling rate of SAR ADCs can be considerably extended while maintaining superior energy efficiency. Nevertheless, the hardware cost expands substantially, which in turn limits the speed/bit-per-cycle of multi-bit SAR ADCs. Compared with its single bit/cycle counterpart, the multi-bit SAR ADC additionally needs to generate multiple references and conduct multi-bit comparisons, posing power, timing, and area overheads. Figure 17.1.1 depicts three prior art techniques for producing the multi-reference with different mechanisms. $\text{In}$ [1] with a $2\mathrm{b}/\text{cycle}$ design, the reference is provided by $2^{\mathrm{M}-1}-1$ capacitive reference DACs $(\text{CDAC}_{\mathrm{R}})$ at $\phi_{\text{REF1}:\mathrm{N}\mathrm{E}\mathrm{F}\mathrm{l}\mathrm{N}}$ where $\mathrm{M}$ and $\mathrm{N}$ denote the number of bit conversions per cycle and the number of cycles, respectively. The 1-then-2b/cycle SAR ADC in [2] utilizes $2^{\mathrm{M}-1}$ capacitive DACs $(\text{CDAC}_{\mathrm{S}})$ to generate the multi-reference. To save the pre-charge time, a fixed 1b conversion must be conducted in the first cycle. $\text{Although}$ these designs secure a fast reference generation, either $\text{CDAC}_{\mathrm{R}}$ or $\text{CDAC}_{\mathrm{S}}$ scales exponentially with $\mathrm{M}$ , preventing high-speed operation with a large $\mathrm{M}$ due to the substantial hardware cost and global reference/input load. The $4\mathrm{b}/\text{cycle}$ design in [3] only requires two $\text{CDAC}_{\mathrm{s}}$ , with the multi-reference realized by level-shifting of the residue voltage with an interpolator. However, the resistive interpolator is supported by two static $\text{open}-\text{loop}$ amplifiers whose linearity and settling accuracy are critical, eventually occupying a $\text{long}$ time before comparison. This work describes $\mathrm{a} \ 5\mathrm{b}/\text{cycle}$ SAR ADC with one signal DAC facilitated by a time-domain quantizer (TD QTZ). The proposed linearized dynamic integrator-based voltage-to-time $(\mathrm{V}2\mathrm{T})$ buffer enables $\text{a high}$ -speed multi-bit/cycle operation, which simultaneously provides isolation between the TD QTZ and sampling front end, thus not only removing kickback noise from the QTZ but rendering a high input bandwidth (BW). With $2\times -\text{time}$ interleaving, the $28\text{nm}$ prototype aggregates a sampling rate of 2.8GS/s and consumes $18\text{mW}$ under $\mathrm{a}\ 0.9\mathrm{V}$ supply. The SNDR and SFDR at Nyquist input are 51. $79\text{dB}$ and 72. $36\text{dB}$ , respectively, leading to a 20. $3\text{fJ}/\text{conv}$ . -step Walden $\text{FoM}$ .