D6CIM: 60.4-TOPS/W, 1.46-TOPS/mm2, 1005-Kb/mm2 Digital 6T-SRAM- Based Compute-in-Memory Macro Supporting 1-to-8b Fixed-Point Arithmetic in 28-nm CMOS

ESSCIRC 2023- IEEE 49th European Solid State Circuits Conference (ESSCIRC)(2023)

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摘要
This paper presents a digital 6T-SRAM-based compute-in-memory macro named D6CIM, which can support 1-to-8b fixed-point arithmetic. Based on the time-sharing (reuse) architecture, D6CIM is designed with three new techniques: static dual- wordline access, hybrid compressor adder tree, and bit-first accumulation. D6CIM is prototyped in 28-nm CMOS. The measurement results show that D6CIM advances the prior arts in the product of the three key metrics: energy efficiency, weight density, and compute density.
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关键词
Compute-in-memory,in-memory-computing,SRAM,deep convolutional neural networks,digital
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