A 0.9V 0.1-4GHz LNTA in 28-nm CMOS Achieving +11.3dBm IIP3 With Self-loaded Linearization Technique

In this paper, a wideband low-noise transconductance amplifier (LNTA) with self-loaded linearization technique is proposed to meet the strong linearity requirements in receiver front-end. The LNTA with proposed technique is implemented in a 28 nm CMOS process and operates from 0.1-4GHz with 13.9-15.1dB gain and 1.2-1.8dB noise figure while drawing 6.8mA from 0.9V supply voltage. It is shown that the proposed LNTA with self-loaded linearization technique achieves more than 10dBm IIP 3 improvement at the cost of only 0.5mA increase in power consumption.