A Compact LNA with 23.3 dB Gain and 3.4 dB NF for V-Band Phased Array Systems in 65-nm CMOS Technology

This paper presents a compact V-band low noise amplifier (LNA) employed stability enhancement and optimized transformer-based matching technique. The LNA is composed of two pseudo-difference common-source stages structure. Each stage adopts the neutralizing capacitor technology to optimize the noise figure and employ the transformer-matching network for a compact footprint. The proposed LNA is implemented in a 65-nm CMOS technology and consume a DC power of 38 mW at a sup-ply of 1.2 V. The amplifier achieves a 23.3 dB gain with a 3-dB bandwidth between 48.3 and 55.8 GHz. At 52 GHz, the optimum noise figure (NF) is 3.4 dB and is below than 3.65 dB over the whole band. Thanks to the compact transformer-based matching network, the LNA achieves a core chip size of only 0.09 mm ² ,