A Capacitorless External-Clock-Free Fully Synthesizable Digital LDO With Time-Based Load-State Decision and Asynchronous Recovery

This article presents an external-clock-free fully synthesizable digital low-dropout regulator (DLDO) without an output capacitor. To lower quiescent current in a steady state, time-based load-state decision is exploited to change an internal clock frequency depending on a load state, while employing a single comparator, a single reference voltage, and a single delay line. In addition, for small voltage droop and short settling time without an output-load capacitor, a asynchronous response to voltage droop and a fast-recovery technique are exploited using a load-direct droop detector and a coarse controller. Besides, in order to obtain full synthesizability, all circuits including pass gates are made up of industry-standard cells and all blocks are implemented using a commercial script-based auto place-and-route tool. The DLDO prototype fabricated in a 40-nm CMOS process occupies a total area of 0.0035mm(2). When load current is changed from 0.78 to 39.2mA with 2.2-ns edge time, voltage droop and settling time are measured as 98 mV and 5 ns, respectively. Thanks to the full synthesizability and the output-capacitor-free design, 16.1-A/mm(2) current density is achieved, which is the best performance compared to prior state-of-the-art DLDOs.