Growth of high-quality $> 10\ \boldsymbol{\mu} \mathbf{m}$-thick GaN-on-Si with low-dislocation density in the order of 107/cm2

Toshiki Hikosaka,Jumpei Tajima, Hajime Nago, Toshiyuki Oka, Shinya Nunoue

2019 Compound Semiconductor Week (CSW)(2019)

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摘要
Epitaxial growth of GaN on Si substrates has been regarded as attractive technology to realize low-cost GaN-based optical and electronic devices. With regard to the practical application of GaN-on-Si, fabrication of thick-GaN layer with low-threading dislocation density is one of the most important challenges. In this study, we demonstrate high-quality >10 μm-thick GaN-on-Si with low-dislocation density in the order of 10 7 /cm 2 . By using Si engineered substrate consists of thin Si(111) layer formed on support substrate with the coefficient of thermal expansion (CTE) matched to GaN, the thermal tensile strain generated in the post-growth cooling process has been mitigated. From the EBSD strain analysis, it is confirmed that the strain in the GaN layer is smaller compared with that in the conventional GaN-on-Si. Using this technology, the 30 μm-thick crack-free GaN layer can be achieved without any interlayers. In order to reduce the dislocation, we utilize the dislocation reduction layer contained with multi-stacked SiN nano-masks and GaN islands. As a result, the low-dislocation density of 7×10 7 /cm 2 in the 10 μm-thick crack-free GaN layer has been achieved. This thick GaN-layer with low-dislocation density have a promise of realizing cost-effective GaN-on-Si based power devices.
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crack-free GaN layer,thin Si(111) layer,thermal expansion coefficient,thermal tensile strain,EBSD strain analysis,cost-effective GaN-on-Si based power devices,GaN islands,dislocation reduction layer,post-growth cooling process,Si engineered substrate,low-threading dislocation density,thick-GaN layer,low-cost GaN-based,low-dislocation density,size 107.0 cm,GaN-Si,Si
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