Saturation thickness of stacked SiO₂ in atomic-layer-deposited Al₂O₃ gate on 4H-SiC

High-k materials as an alternative dielectric layer for SiC power devices have the potential to reduce interfacial state defects and improve MOS channel conduction capability. Besides, under identical conditions of gate oxide thickness and gate voltage, the high-k dielectric enables a greater charge accumulation in the channel region, resulting in a larger number of free electrons available for conduction. However, the lower energy band gap of high-k materials leads to significant leakage currents at the interface with SiC, which greatly affects device reliability. By inserting a layer of SiO2 between the high-k material and SiC, the interfacial barrier can be effectively widened and hence the leakage current will be reduced. In this study, the optimal thickness of the intercalated SiO2 was determined by investigating and analyzing the gate dielectric breakdown voltage and interfacial defects of a dielectric stack composed of atomic-layer-deposited Al2O3 layer and thermally nitride SiO2. Current–voltage and high-frequency capacitance–voltage measurements were performed on metal–oxide–semiconductor test structures with 35 nm thick Al2O3 stacked on 1 nm, 2 nm, 3 nm, 6 nm, or 9 nm thick nitride SiO2. Measurement results indicated that the current conducted through the oxides was affected by the thickness of the nitride oxide and the applied electric field. Finally, a saturation thickness of stacked SiO2 that contributed to dielectric breakdown and interfacial band offsets was identified. The findings in this paper provide a guideline for the SiC gate dielectric stack design with the breakdown strength and the interfacial state defects considered.