Energy-Efficient BLAS L1 Routines for FPGA-Supported HPC Applications.

Vector-based calculations dominate computations in scientific and industrial HPC software. However, up to now there are limited options for mapping them quickly and efficiently on FPGA-supported systems. This work presents a first set of FPGA kernels for mapping a large set of the BLAS L1 routine set on HPC FPGAs. All kernels retain exactly the same interface with respect to their software counterpart routine, whereas they can be configured in terms of internal computing engines. Results show that our kernels can achieve a speed up and performance-per-Watt ratio of up to 7 $$\times $$ and 45 $$\times $$ respectively, compared to Intel’s MKL routines when executed on server-class machines.