Design of soft error correction flip-flop cells for highly reliable applications

With the development of technology, the vulnerability of integrated circuits to Single Event Effect (SEE) increases, and the sensitivity of flip-flops to soft errors induced by Single Event Transient (SET) and Single Event Upset (SEU) increases. Fault tolerant design is necessary for high reliability applications. In this work, a Soft Error Correction Flip-Flop 1(SEC FF1) is proposed, which can correct soft errors induced by SET and SEU at low clock phase without additional clock cycle. It has the lowest area and power consumption overhead and the lowest Power-Delay Product (PDP) compared with other radiation hardened flip-flops. In order to correct soft errors earlier, a variant of SEC FF1, SECFF2, is proposed at the cost of power consumption and switching delay. As the feature size of transistors shrinks, Double Node Upset (DNU) induced by single-event charge sharing is becoming an emerging reliability challenge. In order tolerate DNU, variant of SEC FFs, DNU Correction (DNUC) FFs, are proposed. In addition, the delay element used in the radiation-hardened flip-flops is also introduced.