Ultra low power robust 12t sram architecture based on parallel cross-coupling feedback

Ultra-low power, low on-chip processing circuits are highly desirable for lightweight and wearable applications. Memory is an integral part of most of these systems and is also diminished as the scale of the system reduces. Low power and processing architecture at high speed is therefore a major concern. The durability of random static access memory cells (SRAM) is another critical factor. This paper provides a new standard memory cell based (SCM) twelve-transistor (12 T) circuit. In order to achieve high region performance and low energy usage, three gating transistors for each column of SRAM cells have been used. The three-stage read-out system eliminates reading delays as well as energy consumption. As compared to the previously published SCM circuit in a 65-nm CMOS technology, the read and write energy consumption per operation is reduced. In comparison to the previously published SCM circuit, read time and cell lay-out are also reduced . In comparison, the traditional T-architecture guarantees high data consistency and writes functionality with the proposed 12 T SRAM module.