A 10-bit 563-fs Step Constant-Slope Digital-to-Time Converter in 40-nm CMOS With Nonlinearity Cancellation and Range Extension Techniques

This paper presents a power-efficient constant-slope digital-to-time converter (DTC) with embedded nonlinearity cancellation. By utilizing the capacitor based digital-to-analog converter (C-DAC) to adjust the initial voltage of the discharging process, the DTC achieves a fine resolution of<600-fs. Sources of nonlinearity are quantitatively analyzed, followed by circuit implementations that intrinsically cancel them. The range-extension technique is proposed to increase the range of the DTC by a factor of two without further complicating the capacitor array. The power consumption of the DTC is reduced by the self-power down technique that automatically detects the end of the conversion and shuts off the current. The proposed DTC consumes 120-mu W at 50-MHz clock rate. It achieves a finere solution of 563-fs over a 10-bit range. The measured differential non linearity(DNL)and integral non linearity (INL) are 0.14/0.96-LSB, respectively.