A 27.2–31.2 GHz 92-fs rms Integrated Jitter, Fractional-$N$ Subsampling PLL Using Phase Rotating Technique in 65-nm CMOS

This article presents a fractional- $N$ subsampling PLL (FN-SSPLL) with a phase rotation (PR) technique. The proposed PR-based FN-SSPLL has high output frequency resolution, low phase noise, and low rms jitter. In addition, it obtains an output frequency of fractional times by dithering the phase of the signal fed back into the voltage-controlled oscillator (VCO) to increase the resolution of the output frequency by using sigma-delta modulator (SDM) on the phase-locked loop (PLL). By adopting a subsampling structure, the proposed FN-SSPLL can improve in-band phase noise by $N^{2}$ compared to standard PLLs, and the PR technique can attenuate SDM noise to improve out-of-band phase noise. The proposed PR-based FN-SSPLL was fabricated in a TSMC 65-nm RF CMOS process. The operating frequency range is 27.2–31.2 GHz and the frequency resolution is 24 Hz. Moreover, the reference frequency is 100 MHz and the phase noise is $-$ 104.67 dBc/Hz at 400-kHz offset frequency when the carrier frequency is 29.1 GHz. Finally, the measured rms jitter from 1 kHz to 10 MHz is 92 fs, the total power consumption is 23 mW, the supply voltage is 1 V, and the FoM $_j$ is $-$ 247.1 dB.