A novel hybrid method to integrate delicate MEMS components into a FOWLP

A steep increase in IoT- and smart devices fuels the need for ever more miniaturized and highly integrated microelectronic packages. Fan-Out technology is well suited for this task, as it allows for heterogeneous (co-)integration of sensor elements and corresponding circuitry. Following a Chip-First approach in Fan-Out Wafer-Level Packaging (FOWLP), protection of delicate sensor areas during compression molding and formation of redistribution layers (RDL) becomes a key part of the manufacturing process chain. Such areas include thin membranes, antireflective coatings, air bridges or media access for gas sensors. We demonstrate a novel packaging method for a MEMS pressure sensor with corresponding ASIC (application-specific integrated circuit). We integrate vertical interconnect elements (VIE), instead of employing laser drilling for via formation and thereby avoid debris and reduce the overall package thickness. The hybrid approach, at heart, relies on a structured adhesive layer, onto which components are placed prior to compression molding. Due to its thermal and mechanical stability, the patterned thin film adhesive serves as a (first) dielectric layer. Process development includes warpage management to allow for laser debonding from temporary glass carriers and RDL processing compatible with delicate MEMS surfaces. Summarizing, we present a novel process variant to avoid common issues related to sensor surface integrity using Fan Out technology and thus allow for highly miniaturized System in Package (SiP) concepts with sensor integration by mold embedding.