A SiC MOSFET Current Balancing Technique Based on the Gate Driver with a Multi-channel Output Stage

The improvement of the current handling capacity necessitates the parallel connection of power semiconductors in multichip power modules (MPMs). Derating is a common engineering practice by constraining chips in a narrower operating envelope to address the uneven current sharing and non-homogeneous thermal conditions among paralleled chips. This paper investigates the uneven current sharing issue for paralleled devices and how this can be mitigated using a gate drive with a multi-channel output stage. In particular, the conventional gate drivers incorporating an output stage with a single-buffer layer (SBL) is evaluated and compared to that with a multi-buffer layer (MBL), it is found that the driver structure proposed in this paper can reduce the uneven current sharing in parallel devices by constraining the ground loop current.