P‐8.8: High Performance Video Stream Codec for High‐speed Digital Transmission in Display Driver Chips

Nowadays, as the vivid visual enjoyment requiring in mobile display devices exploding everywhere, enormous bandwidth pressure lands in all high-speed digital transmission interfaces, such as HDMI, MIPI, DP, eDP etc. A low latency in pixels’ time, flexible implementation for circuits, and high performance in visual quality video stream encoder and decoder (FHP-Codec) is proposed to relax the stress. The image structural features are analyzed, which directs an accurate 1D or 2D prediction reducing the redundancy utmost compared with DSC by 10~20% benefit in entropy, without obvious increments in circuit area and power consumption. According to the benchmark in Kodak image suite, FHP-Codec shows a considerable cost-performance ratio for display driver application fields.