Cortex-M0+-based Pacemaker: CMOS Technologies Benchmark to Achieve Ultra-Low Power Operations

Continuous progresses in biotechnology and microelectronic are constantly pushing the limits of miniaturization and power consumption for active implantable medical devices such as pacemakers. Implanted pacemakers are battery operated embedded systems for which autonomy is an important constraint to extend the device lifetime. However, the pacemaker’s processor consumes most of the battery energy since it must analyse in real time the heart activity. Thus, the choice of the appropriate CMOS technology for the processor manufacturing is a crucial point. In this context, this paper proposes a method to mainly estimate ARM-based processor power consumption. This method has been applied to three manufacturing technologies from STMicroelectronics. Simulation results show that considering a temperature of 27°C, the average leakage powers consumed by a Cortex-M0+ for HCMOS9A (1.2 V), CMOS065 (1 V) and FDSOI (1 V) technologies are respectively 300 nW, 136 nW and 486 nW and the active energies are respectively 398 µW/MHz, 49.9 µW/MHz and 20.3 µW/MHz. However, the FDSOI technology can obtain leakage power consumption similar to the CMOS065 one by reducing the supply voltage to 0.8 V. Finally, regarding the power consumption, the area, and the price criteria, the CMOS065 seems to be the technology which offers the best compromise regarding power dissipation, area, and cost, even if an increase of 10 °C has led to an average leakage power increase between 30% and 54,5% for the three technologies.